Group Photos
2003
Department of Defense (DoD) Grant/Contract Final Reports
- K.K. Parhi, "Concurrent Architectures for VLSI Signal and Image Processing," ARO Final Report, November 1, 1993
- K.K. Parhi, "Design Tools and Architectures for Dedicated Digital Signal Processing (DSP) Processors," DARPA/AFRL Final Report, July 1, 1996
- K.K.
IEEE Standards Committee Presentations
- K. K. Parhi, C. Lutkemeyer, A. Abnous, M. Hatamian, "Parallel Implementation of the DSP Functions of the PAM-5 10 Gb/s Transceiver," IEEE 802.3ae Plenary Meeting, March 2000
- O. Agazzi, V. Gopinathan, K. Parhi, K. Kota, A.
Conference Abstracts (Without Proceedings)
2025
- A. Wang, W. Tan, Z. Xu, T. Wei, C. Ding, K. Parhi, Y. Lao, "HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With High-Speed Fixed-Point Approximation," Proc. of Int. Symp. on Field-Programmable Gate Arrays, Feb.
Refereed Conference Publications
2026 and in Press...
- K.K. Parhi, "An Iterated Hybrid Fast Parallel FIR Filter," Proc. of 2026 IEEE Symposium on Circuits and Systems (ISCAS), pp. 1719-1723, Shanghai, China, May 2026
- M. Huang, S.-W. Chiu, and K.K.
Journal Publications
2026 and In Press
- S.-W. Chiu and K.K. Parhi, "Efficient Decomposition of Multistage Composite Length FFT for Complex and Real Signals," IEEE Transactions on Signal Processing, 74, pp. 892-903, 2026
- A. Sodhani and K.K.
Book Chapters
- S. Roychowdhury, D. Koozekanani, M. Reinsbach and K.K.
Past Research Interests
VLSI Digital Filters
Our research in this area has been directed towards design of concurrent algorithms and architectures for VLSI digital filters. In 1960s and 1970s, digital signal processing algorithms were implemented using the available microprocessors which executed the algorithms sequentially. Therefore, there was no motivation for designing concurrent signal processing algorithms, which could exploit pipelining or parallelism.